Large scale integrated arrays of standard cells interconnected in various configurations are well known. Universal arrays of logic gates are also known and consist of a fixed placement of semiconductor logic devices and tunnels arranged in a repetitive ordered structure on a substrate typically silicon or sapphire. All device nodes (gates, drains, sources and tunnel ends) are accessible and by means of a metallization mask, a predetermined metallization pattern of interconnects is laid down for implementing a particular circuit configuration. Typical examples of this type of technology are shown and described in th following patents: (a) U.S. Pat. No. 3,365,707, entitled, "LSI Array and Standard Cells", issued Thomas R. Mayhew on Jan. 23, 1968; (b) U.S. Pat. No. 3,638,202, entitled, "Access Circuit Arrangement for Equalized Loading in Integrated Circuit Arrays", issued to Paul R. Schroeder on Jan. 25, 1972; and (c) U.S. Pat. No. 4,161,662, entitled, "Standardized Digital Logic Chip", issued to Robert B. Malcolm, et al on July 17, 1979.
While the various arrangements as shown and described in these references all have one thing in common, that is, an orderly uniform arrangement of standard logic cells with intermediate cross-over and cross-under power and data interconnects, they do not lend themselves to automatic layout techniques. This is due to the fact that the relative inaccessibility of the basic internal cells and the adjoining roadbed interconnect routing area do not lend themselves to an optimization of metal routing on a single level for interconnecting the devices in a particular logic configuration as desired by the circuit designer.
It is an object of the present invention, therefore, to provide an improvement in large scale integrated arrays fabricated on a semiconductor substrate.
It is a further object of the present invention to provide a universal array of uncommitted semiconductor devices having optimum pin accessibility.
Still a further object of the present invention is to provide an automatic universal array particularly adapted for automated layout techniques which is adapted to implement a single level of interconnects to a plurality of logic gates by an optimum routing pattern.